1. Field of the Invention
The present invention relates to a phase-locked loop circuit for obtaining a new synchronizing signal on the basis of a video synchronizing signal externally supplied to a video display device and, more particularly, to a phase-locked loop circuit (to be referred to as a PLL circuit hereinafter) in a video display device such as a computer.
2. Description of the Prior Art
Conventionally, in deflection processing of a video display device for processing a video signal, a synchronizing signal is used as a reference timing for deflection. However, even in use of the synchronizing signal, no perfect synchronous screen can be obtained as far as only the frequencies are made to match by automatic frequency control, and the phases also need be locked.
For this purpose, a PLL circuit for obtaining a new synchronizing signal in correspondence with an input video synchronizing signal is used. By using the PLL circuit, the operation of the video display device is synchronized with the video signal, thereby realizing a perfect synchronous screen. Such a technique is disclosed in, e.g., FIG. 4 of Japanese Unexamined Patent Publication No. 5-90957.
FIG. 1 is a block diagram showing the arrangement of a conventional PLL circuit. As shown in FIG. 1, the conventional PLL circuit has a phase comparator 1 having two input terminals to compare the phase of an input signal with that of a reference signal. A horizontal sync input signal HS for horizontal scanning is supplied to one input terminal of the phase comparator 1 and compared with a reference signal HREF supplied to the other input terminal. The phase comparator 1 outputs an output signal PFD. The output signal PFD from the phase comparator 1 is supplied to the control input terminal of a voltage-controlled oscillator (VCO) 3 through a low-pass filter (LPF) 2. The oscillation outputs from the VCO 3 are counted by a counter 4. The count value is supplied to a decoder circuit 5. The counter 4 and the decoder circuit 5 are used to count the oscillation outputs from the VCO 3 and set the reference signal HREF having the period (to be referred to as a horizontal period hereinafter) of the above-described horizontal sync input signal HS. The decoder circuit 5 resets the counter 4 when the count value of the counter 4 equals a predetermined value corresponding to the horizontal period.
That is, the counter 4 operates at the horizontal period, and the reference signal HREF having the horizontal period is output from the decoder circuit 5. The reference signal HREF having the horizontal period is supplied to the other input terminal of the phase comparator 1, and its phase is compared with that of the horizontal sync input signal HS. The output signal PFD output from the phase comparator 1 as an error voltage is supplied to the VCO 3 through the LPF 2. By controlling the oscillation frequency of the VCO 3, automatic frequency control for the horizontal sync input signal HS is performed.
This PLL circuit changes the oscillation frequency of the VCO 3 such that the phase difference between the horizontal sync input signal HS and the reference signal HREF having the horizontal period is minimized, so the reference signal HREF is synchronized with the horizontal sync input signal HS. In this state, the PLL circuit is locked, and stable phase control is performed.
FIG. 2 is an input/output timing chart of the phase comparator shown in FIG. 1. As shown in FIG. 2, when the PLL circuit is locked, and a continuous horizontal sync input signal HS is input as an input signal, the phase comparator 1 outputs no phase difference from the reference signal HREF and fixed in a high-impedance state. Therefore, the PLL circuit continues a stable operation.
However, for the synchronizing signal externally input to the video display device, the horizontal sync signal HS and the vertical sync signal are not always completely separated. A composite sync signal in which the horizontal sync signal HS is superposed on the vertical sync signal may be input as an input signal.
FIG. 3 is an input/output timing chart when a composite sync signal is input to the phase comparator shown in FIG. 1. As shown in FIG. 3, when a discontinuous synchronizing signal, i.e., a composite synchronizing signal HVS is input as an input synchronizing signal, the PLL circuit may erroneously operate.
The synchronizing signal at the horizontal scanning period is input to the PLL circuit without removing vertical sync signal components containing an equalizing pulse or a serrated pulse. For this reason, during a period when a vertical sync signal is input, the output PFD from the phase comparator 1 of the PLL circuit changes, and accordingly, the oscillation frequency of the VCO 3 also changes, and the locked state of the PLL circuit is canceled. As a result, the discontinuous composite synchronizing signal HVS causes an erroneous operation of the PLL circuit for receiving the horizontal sync component of the video signal.
As a general means for preventing the erroneous operation of the PLL circuit, the input signal to be supplied to the phase comparator 1 is replaced with another signal having the same period during a time interval when superposition of the vertical sync signal will pose a problem. A PLL circuit which replaces the input synchronizing signal with another signal having the same period to prevent the erroneous operation of the phase comparator 1, and the operation of the PLL circuit will be described below with reference to FIGS. 4 and 5.
FIG. 4 is a block diagram showing a PLL circuit of another prior art. FIG. 5 is a timing chart showing signals so as to explain the normal operation of a phase comparator shown in FIG. 4. The same reference numerals and symbols as in the prior art shown in FIG. 1 denote the same circuits and signals in FIG. 4, and a detailed description thereof will be omitted.
As shown in FIGS. 4 and 5, for this PLL circuit, a vertical synchronous separation circuit 7 and a selector 6 are added to the circuit shown in FIG. 1. Especially, the selector 6 is arranged, on the input side of a phase comparator 1 for receiving an input synchronizing signal, to select a composite synchronizing signal HVS or a reference signal HREF in accordance with a selection pulse SEL obtained by separating the vertical sync component from the composite synchronizing signal HVS by the vertical synchronous separation circuit 7. The selector 6 replaces the composite synchronizing signal HVS as an input signal with the reference signal HREF during a period designated by the selection pulse SEL. More specifically, in the vertical synchronizing period when a phase error occurs due to input of the vertical sync component of the composite synchronizing signal HVS, the reference signal HREF is input to both terminals of the phase comparator 1, so the output side of the phase comparator 1 is kept fixed in the high-impedance state. That is, since no phase error output PFD is output, the output from a VCO 3 is prevented from changing such that the locked state of the PLL circuit is not canceled.
In this manner, the composite synchronizing signal HVS is replaced with the reference signal HREF and input to the phase comparator 1. In this case, in progressive scanning as one of image scanning schema, i.e., when one-horizontal (1H) interval is inserted between a horizontal sync signal component and a vertical sync signal component of the composite synchronizing signal HVS, and no equalizing pulse component is input, the phase comparator 1 can normally operate.
However, in interlaced scanning, i.e., when only a 1/2 horizontal (1/2 H) interval is set between a horizontal sync signal component and a vertical sync signal component, or when an equalizing pulse component is input, the erroneous operation of the phase comparator 1 during the vertical synchronizing period cannot be completely prevented only by replacing the composite synchronizing signal HVS with the reference signal HREF.
FIG. 6 is a timing chart showing signals so as to explain the erroneous operation of the phase comparator shown in FIG. 4. As shown in FIG. 6, a horizontal sync signal and a vertical sync signal of the composite synchronizing signal HVS are separated at an interval corresponding to only 1/2 horizontal period (1/2 H), and an equalizing pulse component is input. In this case, the vertical sync signal component of the composite synchronizing signal HVS is input at the 1/2 horizontal period (1/2 H). In addition, the composite synchronizing signal HVS is replaced with the reference signal HREF after input of the vertical sync signal component. For this reason, the phase comparator 1 outputs the phase error output PFD before and after the replacement, resulting in an erroneous operation.
In the above-described conventional PLL circuit, when the horizontal sync signal and the vertical sync signal are separated at only 1/2 horizontal period (1/2 H), as in interlaced scanning, or when an equalizing pulse component is inserted into the vertical sync signal, the erroneous operation of the phase comparator during the vertical synchronizing period cannot be completely prevented only by replacing the composite synchronizing signal HVS with the reference signal HREF. The reason has been described above. The vertical sync signal component of the composite synchronizing signal HVS is input at the 1/2 horizontal period (1/2 H), and replacement with the reference signal HREF is performed after input of the vertical sync signal component. For these reasons, during this period, phase locking to the reference signal HREF cannot be performed, and the phase error voltage is output from the phase comparator.